In semiconductor manufacturing, a yield ramp for a product, i.e., chip, represents the yield of the product as a function of time beginning with production of the first product unit. It is desirable to maximize the gradient of the yield ramp, i.e., optimize the product yield ramp, so that the product reaches a mature state of production at the earliest possible time. To optimize the product yield ramp it is useful to characterize the product defectivity and systematic loss mechanisms that detract from product yield. However, as technology moves into deeper submicron regimes, manufacturing variation is becoming more significant in detracting from achievement of high product yields. Therefore, to facilitate yield ramp optimization at the deeper submicron technology nodes, solutions are needed to better characterize product yield variability as it relates to the manufacturing process.